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description available in pga (puma 2), jlcc (puma 67) and gullwing (puma 77) footprints, the puma **e4001 is a 4 mbit eeprom module user configurable as 128k x 32, 256k x 16 or 512k x 8. available with access times of 120, 150 and 200ns, the device features hardware and software data protection, 10,000 cycle write/erase capability and 10 year data retention time. an option of independant (a version) or single we control is available. parts may be screened in accordance with mil- std-883 pin functions a0~a16 address input d0~d31 data inputs/outputs cs1~4 chip select we1~4 write enables oe output enable vcc power (+5v) gnd ground features ? 4 megabit eeprom module. ? access times of 120/150/200 ns. ? output configurable as 32/ 16/ 8 bit wide. ? upgradeable footprint ? operating power 1600/ 830/ 445 mw (max). low power standby 2.2 mw (max). ? byte and page write (128 bytes) in 5ms typical with data polling and toggle bit indication of end of write. ? hardware and software data protection. ? puma 2 - 66 pin ceramic pga. ? puma 67 - 68 lead ceramic jlcc. ? puma 77 - 68 lead ceramic gullwing. ? may be screened in accordance with mil-std-883. ? 100,000 w/e cycle endurance option block diagram puma 67e4001 and 77e4001 block diagram puma 2e4001, 67e4001a and 77e4001a 128k x 32 eeprom module puma 2/67/77e4001/a - 12/15/20 issue 4.2 : november 1998 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe we a0~a16 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe we1 a0~a16 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom we2 we3 we4 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 2 recommended operating conditions min typ max dc power supply voltage v cc 4.5 5.0 5.5 v input low voltage v il -1.0 - 0.8 v input high voltage v ih 2.0 - v cc +1 v operating temp range t a 0-70 c t ai -40 - 85 c ( i suffix) t am -55 - 125 c ( m , mb suffix) absolute maximum ratings (1) operating temperature t opr -55 to +125 c storage temperature t stg -65 to +150 c input voltages (including n.c. pins) with respect to gnd v in -0.6 to +6.25 v output voltages with respect to gnd v out -0.6 to v cc +0.6 v notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (t a =25c,?=1mhz) note: these parameters are calculated, not measured. parameter symbol test condition typ max unit input capacitance cs1~4, we1~4 (1) c in1 v in =0v - 20 pf other inputs c in2 v in =0v - 22 pf output capacitance c out v out =0v - 22 pf notes: (1) on the puma 2e4001, 67e4001a, 77e4001a versions only. dc operating conditions dc electrical characteristics (t a =-55c to +125c,v cc =5v 10%) parameter symbol test condition min max unit input leakage current i li1 v in = gnd to v cc +1 -40a output leakage current 32 bit i lo v i/o = gnd to v cc , cs (1) =v ih -40a operating supply current 32 bit i cc32 cs (1) =oe=v il , we=v ih , i out =0ma, ?=5mhz (2) - 320 ma 16 bit i cc16 as above - 166 ma 8 bit i cc8 as above -89ma standby supply current ttl levels i sb1 cs (1) = 2.0v to v cc +1v -12ma cmos levels i sb2 cs (1) = v cc -0.3v to v cc +1v - 1.2 ma output low voltage v ol i ol = 2.1ma. - 0.45 v output high voltage v oh i oh = -400a. 2.4 - v notes (1) cs above are accessed through cs1~4. these inputs must be operated simultaneously for 32 bit operation, in pairs in 16 bit mode and singly for 8 bit mode. (2) also for we1~4 on the puma 2e4001, 67e4001a, 77e4001a versions. additionally, we1~4 are accessed as in note (1) above.
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 3 ac test conditions output test load * input pulse levels: 0v to 3.0v * input rise and fall times: 10ns * input and output timing reference levels: 1.5v * output load: 1 ttl gate + 100pf * v cc =5v10% write cycle parameter symbol min typ max unit write cycle time t wc --10 ms address set-up time t as 0- -ns address hold time t ah 50 - - ns output enable set-up time t oes 0- -ns output enable hold time t oeh 0- -ns chip select set-up time t cs 0- -ns chip select hold time t ch 0- -ns write pulse width t wp 100 - - ns write enable high recovery t wph 50 - - ns data set-up time t ds 50 - - ns data hold time t dh 0- -ns byte load cycle t blc - - 150 s ac operating conditions read cycle 12 15 20 parameter symnbol min max min max min max unit read cycle time t rc 120 - 150 - 200 - ns address access time t aa - 120 - 150 - 200 ns chip select access time t cs - 120 - 150 - 200 ns output enable access time t oe 0 600 70 0 80ns cs or oe to output float (2) t df 0 600 70 0 80ns output hold from address change t oh 0-0-0 -ns notes: (1) t hz max. and t olz max. are measured with cl = 5pf, from the point when chip select or output enable return high (whichever occurs first) to the time when the outputs are no longer driven. t hz and t ohz are shown for reference only: they are characterized and not tested. (2) this parameter is characterised and is not 100% tested. 645 100pf i/o pin 1.76v w
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 4 toggle bit characteristics (1) parameter symbol min typ max unit data hold time t dh 10 - - ns oe hold time t oeh 10 - - ns oe to output delay (2) t oe ---ns oe high pulse t oehp 150 - - ns write recovery time t wr 0- -ns notes: (1) these parameter are characterised and is not 100% tested. (2) see ac read characteristics. data polling characterisitics (1) parameter symbol min typ max unit data hold time t dh 10 - - ns oe hold time t oeh 10 - - ns oe to output delay (2) t oe ---ns write recovery time t wr 0- -ns notes: (1) these parameter are characterised and is not 100% tested. (2) see ac read characteristics.
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 5 ac write waveform - we controlled ac write waveform - cs controlled t wc t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph address we oe cs1~4 data t wc t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph address we cs1~4 oe data
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 6 page mode write waveform note: a8 through a16 must specify the page address during each high to low transition of write enable (or chip select). output enable must be high only when write enable and chip select are both low. read cycle timing waveform oe cs1~4 we a0-a16 data t wp t wph t blc t as t ah t dh t ds t wc valid add valid data byte 0 byte 1 byte 2 byte 3 byte 126 byte 127 a0~a16 cs1~4 oe data high z t cs t oe t acc t ohz t oh t rc output valid address valid t clz t olz t ohz
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 7 software protected write waveform oe cs1~4 we/we1~4 a0~a6 t wp t as t ah t dh data t ds t wc byte 0 byte 126 byte 127 05555 02aaa 05555 aa 55 a0 a7~a16 byte address page address t wph blc t toggle bit waveform cs1~4 we/we1~4 oe t oe t oeh t dh t wr d6,d14, d22,d30 high z we/we1~4 cs1~4 oe d7,d15, d23,d31 a0-a16 t oe t oeh t dh t wr an an an an an high z data polling waveform
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 8 device operation the following description deals with the device, with the references to we meaning we1~4 on the 'a' parts. read the device read operations are initiated by both output enable and chip select low. the read operation is terminated by either chip select or output enable returning high. this 2-line control architecture elimanates bus contention in a system environment. the data bus will be in a high impendence state when either output enable or chip select is high. write write operations are initated when both chip select and write enable are low and output enable is high. the device supports both a chip select and write enable controlled write cycle. that is, the address is latched by the falling edge of either chip select or write enable, whichever occurs last. similarly, the data is latched internally by the rising edge of either chip select or write enable, whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5 ms. page mode write the page write feature of the device allows the entire memory to be written in 5 seconds. page write allows 128 bytes of data to be written prior to the internal programming cycle. the host can fetch data from another location within the system during a page write operation (change the source address), but the page address (a8 through a16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write up to 128 bytes in the same manner as the first byte written. each successive byte load cycle, started by the write enable high to low transition, must begin within 150 s of the falling edge of the preceding write enable. if a subsequent write enable high to low transition is not detected within 150 s, the internal automatic programming cycle will commence. data polling the device features data polling to indicate if the write cycle is completed. during the internal programming cycle, any attempt to read the last byte written will produce the compliment of that data on d7. once the programming is complete, d7 will refect the true data. note: if the the device is in a protected state and an illegal write operation is attempted data polling will not operate. toggle bit in addition to data polling, another method is provided to determine the end of a write cycle. during a write operation successive attempts to read data will result in d6 toggling between 1 and 0. once a write is complete, this toggling will stop and valid data will be read. hardware data protection the device provides three harware features to protect nonvololitile data from inadvertent writes. ? noise protection - a write enable pulse less than 15 ns will not inditiate a write cycle. ? default v cc sence - all functions are inhabited when v cc < 3.6 v. ? write inhibit - holding either output enable low, write enable high or chip select high will prevent an inadvertent write cycle during power on or power off, maintaining data integrity.
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 9 mode cs1~4 oe outputs read write standby write inhibit we 0 0 1 x x 1 0 x 1 x 0 i x x 0 data out data in floating software data protection the device can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protect feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the device is also protected against inadvertent and accidental writes in that, the software algorithm must be issued prior to writing additional data to the device. operating modes the table below shows the logic inputs required to control the operation of the device. 0 = v il : 1 = v ih : x = v ih or v il
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 10 notes: (1) data format i/o7-i/o0 (hex); once initiated, this sequence of write operations should not be interrupted. (2) enable write protect state will be initiated at end of write even if no other data is loaded. (3) disable write protect state will be initiated at end of write period even if no other data is loaded. (4) 1 to 128 bytes of data may be loaded. software algorithms selecting the software data protection mode requires the host system to precede datawrite operations by a series of three write operations to three specfic addresses. the three byte sequence opens the page write window enabling the host to write from from 1 to 128 bytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state software data protection algorithm regardless of wheather the device has been protected or not, once the software data protected aglorithm is used and the data is written, the device will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the device will be write protected during power-down and any subsequent power-up. load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 last byte / word to last address load data xx to any address (4) writes enabled (2) enter data protect state
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 11 software data protect disable in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an e 2 prom programmer. the following six step algorithm will reset the internal protection circuit. after t wc , the device will be in standard operating mode. last byte / word to last address load data xx to any address load data 20 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 (4) exit data protect state (3)
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 12 package details puma 67e4001 24.99 (0.984) sq. 24.89 (0.980) sq. (0.202) max r=0.76 (0.030) typ. 1.27 (0.050) typ. 0.64 (0.025) min 21.08 (0.830) 0.43 (0.017) typ. 0.10 (0.004) 25.40 (1.000) sq. 24.49 (0.964) sq. 1.35 (0.053) 0.94 (0.037) 5.13 20.57 (0.810) sq. 20.07 (0.790) sq. 24.13 (0.950) sq. 23.11 (0.910) sq. 21.37 (0.840) 0.10 (0.004) 24.13 (0.950) sq. 20.57 (0.810) sq. 1.27 (0.050) 0.43 (0.017) 1.78 (0.070) 5.44 (0.214) max 25.15 (0.990) sq. 22.61 (0.890) sq. 0.76 (0.030) 24.67 (0.970) sq. 22.10 (0.870) sq. 20.10 (0.790) sq. 23.62 (0.930) sq. puma 77e4001 puma 2e4001 15.24 (0.60) typ 27.58 (1.086) sq 4.83 (0.190) 4.32 (0.170) 1.40 (0.055) 1.52 (0.060) 8.13 (0.320) max 0.66 (0.026) 1.27 (0.050) 2.54 (0.010) typ 2.54 (0.010) typ 1.02 (0.040) 0.53 (0.021) 0.38 (0.015) 1.15 (0.045) 27.08 (1.066) sq
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 13 pin definitions 1 12 23 view from above 213 24 3 14 25 4 15 26 5 16 27 6 17 28 7 18 29 8 19 30 9 20 31 10 21 32 11 22 33 34 45 56 35 46 57 36 47 58 37 48 59 38 49 60 39 50 61 40 51 62 41 52 63 42 53 64 43 54 65 44 55 66 d8 we2 d15 d9 cs2 d14 d10 gnd d13 a13 d11 d12 a14 a10 oe a11 nc a12 we1 nc vcc d7 d0 cs1 d6 d1 nc d5 d2 d3 d4 d24 vcc d31 d25 cs4 d30 d26 we4 d29 a6 d27 d28 a7 a3 a0 nc a4 a1 a8 a5 a2 a9 we3 d23 d16 cs3 d22 d17 gnd d21 d18 d19 d20 a15 a16 nc a0 a1 a2 a3 a4 a5 cs3 gn d cs4 we1 a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 puma 67e4001a view from above vcc a11 a12 a13 a14 a15 a16 cs1 oe cs2 nc we2 we3 we4 nc gnd nc oe cs1 nc a0 a1 a2 a3 a4 a5 cs3 gnd cs4 we a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 puma 67e4001 view from above vcc a11 a12 a13 a14 a15 a16 cs2 nc nc nc nc nc gnd nc puma 67e4001 / puma 77e4001 puma 67e4001a / puma 77e4001puma puma 2e4001
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 14 mb multichip module screening flow screen test method level visual and mechanical internal visual 2010 condition b or manufacturers equivalent 100% temperature cycle 1010 condition c (10 cycles,-65 o c to +150 o c) 100% constant acceleration 2001 condition b (y1 & y2) (10,000g) 100% endurance write cycle endurance and as per internal specification. data retention performance burn-in pre-burn-in electrical per applicable device specifications at t a =+25 o c 100% burn-in t a =+125 o c,160hrs min 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post-burn-in at t a =+25 o c 10% hermeticity 1014 fine condition a 100% gross condition c 100% quality conformance per applicable device specification sample external visual 2009 per vendor or customer specification 100% military screening procedure multichip screening flow for high reliability product is in accordance with mil-883 method 5004 .
issue 4.2 : november 1998 puma 2/67/77e4001/a - 12/15/20 15 puma 2e4001amb-12e blank = 10,000 w/e cycle endurance e = 100,000 w/e cycle endurance speed 12 = 120 ns 15 = 150 ns 20 = 200 ns temp. range/screening blank = commercial temperature i = industrial temperature m = military temperature mb = processed in accordance with mil-std-883 we option blank = single we (puma 67 / 77 only) we1~4 (puma 2 only) a = we1~4 (puma 67 / 77 only) organisation 4001 = 128kx 32, user confiurable as 256k x 16 and 512k x 8 technology e = eeprom memory package puma 2 = jedec 66 pin ceramic pga package puma 67 = jedec 68 j-leaded ceramic surface mount package puma 77 = jedec 68 leaded gull wing ceramic surface mount package ordering information note : although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.

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